1. Field of the Invention
The present invention relates to a printed circuit board in which a circuit pattern is formed, and particularly relates to a printed circuit board for which the warpage can be reduced even if a phenolic paper substrate is used.
2. Background Art
<A Traditional Printed Circuit Board>
When the pattern of a printed circuit board is designed, traditionally, no limit is set in the ratio of copper foils formed on the front surface and the back surface of the circuit board or copper foil balance.
<In the Case of a Phenolic Paper Substrate>
However, when a phenolic paper substrate (FR1) is used, the board is warped when the traditional pattern design method is used. If the board is being warped, when components are mounted, the following problems will happen. For example, the component is not well soldered, or the component is not in an automatic soldering reflow groove. Moreover, stress among the mounted component, the soldering part and the copper foil is produced due to the warp after the solder is solidified in the reflow groove.
<Related Arts to Prevent a Warp of the Circuit Board>
As a circuit board in view of the above situation, JP-A-2002-261402 discloses to prevent the warp of a circuit board as follows. According to JP-A-2002-261402, the overall area of the circuit pattern provided on the front surface of the circuit board is generally the same as the overall area of the circuit pattern provided on the back surface of the circuit board.
Thereby, the warp of the circuit board becomes extremely small. When an electric component is soldered, the electric component can be soldered surely. Meanwhile, the solder of the electric component can be prevented from being stripped when the electric component is soldered to a mother board or in use.
<Problems of JP-A-2002-261402>
In the method described in JP-A-2002-261402, the overall area of the circuit pattern on the front surface is generally the same as the overall area of the circuit pattern on the back surface, but in many cases, the circuit patterns are formed with sparse parts and dense parts. Therefore, even if the overall areas of the circuit patterns on the front surface and the back surface are the same, it naturally occurs that the sparse part of the circuit pattern on the front surface may correspond to the dense part of the circuit pattern on the back surface, or the dense part of the circuit pattern on the front surface may correspond to the sparse part of the circuit pattern on the back surface. In such a case, a deformation occurs between the front surface and the back surface, and a warp occurs.
<Related Art 2 to Prevent a Warp of the Circuit Board>
JP-A-2009-267162 also discloses to prevent a warp of the circuit board as follows. According to JP-A-2009-267162, a circuit pattern which includes a solid pattern for power supply is formed on the front surface of the circuit board, a circuit pattern which includes a solid pattern for grounding is formed on the back surface of the circuit board, and a plurality of holes are formed in the solid patterns in areas where the two solid patterns are not overlapped (in a top view) to alleviate the stress and control the warp.
<Problems of JP-A-2009-267162>
According to the method described in JP-A-2009-267162, for the solid patterns in the areas where the two solid patterns are not overlapped (in a top view) the stress is alleviated so that the deformation is hard to occur. In areas, however, where the two solid patterns are overlapped in a top view, circuit patterns which include the solid patterns are formed respectively. Since it also naturally occurs that the dense part of the circuit pattern on the back surface may correspond to the sparse part of the circuit pattern on the front surface, like JP-A-2002-261402, deformation in the parts occurs, and a warp occurs.